module Fetch( inst, nxt_pc, rst, clk, target, X_target, Jr, Branch, T, pc_en,
              inst_in, I_Mem_en, I_Mem_wr, createdump );

 input       rst, clk;
 input[15:0] target, X_target;
 input Jr, Branch, T;
 input pc_en;

 input[15:0] inst_in;
 input I_Mem_en;
 input I_Mem_wr;
 input createdump;
 
 output[15:0] nxt_pc;
 output[15:0] inst;
 
 wire[15:0] pc_in;
 wire[15:0] pc_out;

 pc pc0(.rst(rst),
        .clk(clk),
        .pc_en(pc_en),
        .pc_in(pc_in),
        .pc_out(pc_out) );

 assign nxt_pc = pc_out + 16'h0002;

 assign pc_in = (Jr)?                X_target :    //target calculated in the X stage
                (Jump|(Branch & T))?   target : nxt_pc;

 memory2c I_Mem (.data_out(inst),
                 .data_in(inst_in),
                 .addr(pc_out),
                 .enable(I_Mem_en),
                 .wr(I_Mem_wr),
                 .createdump(createdump),
                 .clk(clk),
                 .rst(rst) );
 endmodule
